In source synchronous systems, a sending circuit may send a clock signal to a receiving circuit in order for the receiving circuit to retrieve data. The receiving circuit may use the clock signal to retrieve the data and generate data and clock signals for transmission back to the sending circuit. Upon receipt of the data and clock signals, the sending circuit samples data pulses of the data signals in response to clock edges of the clock signals in order to identify the data values of the data carried by the data signals. In order to correctly identify the data values, the sending circuit relies on the receiving circuit transmitting the clock signals at a target duty cycle (e.g., 50%), and also relies on the receiving circuit transmitting the data and clock signals with proper timing or edge alignment between each other. In the event that the duty cycle of the clock signals is too far from the target duty cycle, or in the event that too much skew exists between the clock and data signals, the sending circuit may not accurately identify the data values.
The receiving circuit may include a clock path extending from an input clock node to an output clock node. The receiving circuit may receive an input clock signal from the sending circuit at the input clock node, and may output an output clock signal to the sending circuit at the output clock node. The clock path may include various circuitry that generates intermediate clock signals based on the input clock signal in order to generate the output clock signal. At some point along the clock path, an intermediate clock signal generated in the clock path may be used to generate the clock and data pulses that are converted into the output clock and data signals, respectively.
The receiving circuit may include a duty cycle correction circuit that measures and corrects for duty cycle distortion in the input clock signal or an intermediate signal generated in the clock path. While such duty cycle correction may help reduce duty cycle distortion in the output clock signal, it would not correct for any extra distortion created in the clock path between the input or intermediate clock signal being measured and the output clock signal at the output clock node. The extra distortion may be insignificant at lower frequencies, but may become problematic as clock frequencies increase into the Gigahertz range and beyond.
Performing localized duty cycle correction of the output clock signal by implementing duty cycle correction circuitry at or near the output clock node may not be feasible. For example, performing localized duty cycle correction may violate data out timing specifications that specify the timing relationships between the clock and data signals. Additionally, the driver and pre-driver circuits used to generate the output clock signal are relatively large circuits that are located close to the output node, such that there is not enough room to also include duty cycle correction circuitry. Also, even if there was enough room, adding additional circuitry may undesirably increase the capacitance on the output nodes, limiting the operating speed. Moreover, the pre-driver and driver circuitry may have separate pull-up (PMOS) and push-down (NMOS) paths to generate a single output clock signal, thus making duty cycle correction for the single output clock signal difficult. Similar obstacles may be present for performing localized skew correction between output clock and data signals. As such, ways to implement duty cycle correction circuits that detect and correct for duty cycle distortion in the output clock signal, and/or skew correction circuits that detect and correct for skew distortion between output clock and data signals, may be desirable.